PHASE MATCHING CIRCUIT

摘要

A phase matching circuit for realizing accurate data transmission and reception through phase shift control only during a data invalid region. The phase matching circuit includes an input buffer (210) for taking first data with a first clock; an output buffer (218) sending second data with a second clock: a phase detector (220) for comparing the phases of first and second clocks and detecting a phase difference within a predetermined value; a phase control unit (216) for directly outputting the first data to the output buffer when the phase difference within the predetermined value is not detected or for outputting the first data phase shifted to the output buffer, and for converting the first data synchronized with the first clock to the second data of the same content as the first data synchronized with the second clock in the same frequency as the first clock: an invalid data region detector (214) for detecting an invalid region of first data; and a phase shifter controller (212) for inhibiting phase shift control in the phase control unit (216) when the invalid data region detector does not detect the invalid region and for allowing phase shift control in the phase control unit when the invalid data region detector detects the invalid region.