发明名称 INTEGRATED PROGRAMMABLE LOGIC ARRAY
摘要 <p>PURPOSE: To stop the consumption of static electric energy by connecting the source of a 1st electric field-effect transistor to reference potential through the drain-source path of a 2nd electric field-effect transistor and to the base of a bipolar transistor arranged between input and output lines. CONSTITUTION: A programming point 11 between an input line Lx and an output line Ly of a logic array 10 consists of two electric field-effect transistors N1 and N2 and a bipolar transistor Q. The gate of the transistor N1 is connected to the input line Lx, the drain is connected to the output line Ly, and the source of the transistor N1 is connected to an earth line Lg via a drain source current path of the transistor N2 whose gate is connected to the output line Ly. The collector of the bipolar transistor Q is connected to the output line Ly, an emitter is connected to the ground line Lg, and a base is connected to a connecting point of the source of the transistor N1 and the drain of the transistor N2. This stops consuming static electric energy.</p>
申请公布号 JPH03241921(A) 申请公布日期 1991.10.29
申请号 JP19900260284 申请日期 1990.09.28
申请人 BULL SA 发明人 JIYORUJIYU NUU
分类号 G11C17/12;G11C16/04;G11C17/00;H03K19/177 主分类号 G11C17/12
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