| 摘要 |
Instruction prefetching apparatus particularly adapted to executing an EXECUTE instruction specifiying a single subject instruction. The apparatus includes a first and second separately-controllable instruction syllable register and control apparatus. Under control of the control apparatus, the first instruction syllable register receives only the first syllable of the prefetched instruction; the second instruction syllable register receives all other syllables. The instruction syllable registers may be loaded either directly from memory or from a data register internal to the CPU. In the first case, the address of the instruction syllable to be prefetched is contained in a special instruction address register which is incremented each time an instruction syllable register is loaded. In the second case, the loading does not affect the value of the instruction address register. Also disclosed is a method of prefetching in which the first instruction syllable is prefetched into the first instruction syllable register and each of the other syllables is prefetched in turn to the second instruction syllable register and a method of executing the EXECUTE instruction in which the syllables of the EXECUTE instruction are prefetched directly from memory using the instruction address and the syllables of the subject instruction are fetched into the data register and from there into the instruction syllable registers.
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