发明名称
摘要 PURPOSE:To reduce the layout area of a circuit by a method wherein a part of a connection wiring between a plurality of I<2>LS is arranged on the base of the pnp transistor of I<2>L through the intermediary of an insulation film. CONSTITUTION:There is a gap between the injector wiring of I<2>L and the base or collector terminal of the pnp transistor thereof. By laying a connection wiring 23 between I<2>Ls through this gap, the number of wirings which have been laid usually on the base of an npn transistor can be reduced, and this method is very effective, in particular, for a cell wherein a collector is wired in parallel to an inductor. By this constitution, an idle space of the npn transistor is reduced, and thereby the layout area of a circuit can be diminished. In addition, it enables the prevention of the useless fall of the current amplification factor of the npn transistor, and the reduction of a junction capacity, and thus the degree of freedom of a design of layout is increased.
申请公布号 JPH0368540(B2) 申请公布日期 1991.10.28
申请号 JP19820118510 申请日期 1982.07.09
申请人 HITACHI LTD 发明人 KANEKO KENJI;INABA TOORU;OKABE TAKAHIRO;WATABE TOMOYUKI
分类号 H01L27/082;H01L21/8226;H01L27/02 主分类号 H01L27/082
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