发明名称 |
DEVICE FOR SYNCHRONIZING THE OUTPUT PULSES OF A CIRCUIT WITH AN INPUT CLOCK |
摘要 |
A device for synchronizing the output test pattern signals (14) of a test circuit with the clock signal (14) of a device under test (DUT). The invention uses a programmable delay (56) in the feedback loop of a phase locked loop system (20) to adjust the phase of the test pattern signals (14) to be synchronized with the clock (12) of the device under test (DUT). |
申请公布号 |
KR910009087(B1) |
申请公布日期 |
1991.10.28 |
申请号 |
KR19880007594 |
申请日期 |
1988.06.23 |
申请人 |
HEWLETT-PACKARD CO. |
发明人 |
REDIG MICHAEL J.;PRATER DAVID M. |
分类号 |
H04L7/033;G01R31/3183;G01R31/319;H03L7/06;H03L7/08;H03L7/081;H03L7/087;H03L7/183;(IPC1-7):H03L7/00 |
主分类号 |
H04L7/033 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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