| 摘要 |
<p>PURPOSE:To make a linear DCT (discrete cosine transformation) processing complete by dividing a bit length into specific bit length sets, executing the calculation of partial product in parallel depending on the bit length and executing the sum of intermediate results finally. CONSTITUTION:The DCT processor is provided with a 14-bit picture signal input u(j)2, 14-bit data registers 3-10 and 14-bit picture signal {u(n=mod(j)s), m=0-7} 11-18. Bit serial arithmetic sections 19-22 employ shift registers to apply addition and subtraction in bit serial. An M-bit length is divided into L bit length sets to satisfy the relation of L<N, the calculation of partial product is executed in parallel in the L bit length and the intermediate results are added finally. Thus, in the case of N=8, J=2, 8X1 linear DCT processing is realized for a period of 8 sampling clocks and the accuracy of the internal arithmetic operation is ensured up to the accuracy of M=14-bit without use of a multiplier.</p> |
