Stacked bit line architecture for high density cross-point memory cell array.

摘要

A stacked bit line architecture utilizing high density cross-point memory arrays (18, 18') forms a DRAM semiconductor memory device (10). The true and complementary bit line pairs (14) connected to the respective memory cell arrays (18, 18') are formed in two metal layers, one above the other. A bit line interconnector region (22) is provided that uses a third metal layer together with the first and second layers to transpose the vertical stacking of each pair and to transpose the planar alignment of adjacent bit line pairs. The DRAM memory cell array (10) has a high density cross-point memory cell architecture that behaves electrically as a folded bit line array. <IMAGE>