| 摘要 |
<p>A switched-current integrator circuit (50) employs track-and-hold circuits (52,54) in which the gates of the current mirror FET switches (M1,M2) are connected together to form a common gate node (58) to double the effective holding capacitance. Additionally, the common gate node (58) is coupled to the input terminal (16) through a CMOS switch (62,64) so that parasitic clock feed-through is essentially cancelled to minimize DC offset voltages (V1,V3 in FIG. 4). <IMAGE></p> |
