| 摘要 |
<p>A reduced noise, data output stage (1) of the buffer type, intended for CMOS logic circuits, comprises pairs (5,6,7) of transistors (M1,M4,M2,M5,M3,M6) connected in parallel with one another between a pair of inputs (2,3) and a data output (4). These transistor pairs (5,6,7) are driven through respective resistive control lines including respective resistors (R1,R2) which are connected between corresponding gate electrodes of the first and the second transistor pairs, and of the second and the third transistor pairs, to reduce the value of the differential ratio dI/dt, while also reducing switching noise. <IMAGE></p> |
