| 摘要 |
The present invention relates to a multiplexing circuit for clock signals, the output signal from this circuit being the clock signal identified by a selection signal. The multiplexing circuit for clock signals is controlled by one selection signal at least. An invariable switching level being one of the two levels of these clock signals, the circuit comprises, for each clock signal, a timing module producing a delayed clock signal taking the value of this clock signal for a first state of the selection signal in the absence of a busy signal as soon as a switching level of this clock signal appears and interrupting this delayed clock signal when the selection signal is in a second state as soon as a switching level of the clock signal appears, control means producing the busy signal as soon as a timing module produces a delayed clock signal, and means for producing, as output signal, the delayed clock signal output by the selected timing module. <IMAGE>
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