Circuit for adjusting voltage level of data output in a semiconductor memory device

摘要

The circuit for adjusting voltage level of data output in a semiconductor memory device, thereby having a high speed in its access time. The improvement comprises a power supply terminal; a ground reference voltage terminal; a data output terminal; a data output driving controller for receiving amplified sensing signals and outputting said signals in response to an enable clock; driving circuitry for outputting data output to the data output terminal in response to the signals outputted from the data output driving controller; control pulse generating circuitry receiving the enable clock, for generating an output data control pulse when the data output is completed by the enable clock; and high-impedance voltage generating circuitry for generating voltage level of high-impedance state in response to the output data control pulse and applying said high-impedance voltage to the data output terminal, whereby the voltage level of the data output terminal is controlled to return unconditionally to the high-impedance voltage level from preceding output voltage level.