| 摘要 |
PURPOSE: To conduct the functional test of a device under such a condition as if the device were actually being used by fitting a register which stores and outputs a testing bit and putting an element of a logic device under a predetermined logic condition forcibly in response to the testing bit. CONSTITUTION: When stacking test with one D type FF to respective desired testing signals is conducted, a shift clock signal SCLK is gated with an activating signal SUB-MODE1 and applied to clock inputs FFD0 -D15 in a testing-type register 82. A series data signal is also gated with the signal SUB-MODE1 and applied to an input of FFD16 . A data bit is inputted in series and shifted until the register is filled. SUB-MODE1 makes the register 82 inoperative to protect the data. The outputs of FFD0 -D15 are gated to AND gates G0 -G15 using the signal TEST. The signals TB0 -TB15 which are attained in this way are applied to the element of a logical device where the test is conducted, and a desired logical style is taken forcibly. |
