| 摘要 |
PURPOSE:To shorten turnaround time by forming a depletion type semiconductor region of first conductivity type, connecting between the source and drain regions of MISFETs below the second conductivity type channel regions of first conductivity type MISFETs, implanting second conductivity type impurity ions through the gate electrode of a a selected MISFET into the channel regions, and rendering them enhancement type. CONSTITUTION:An n<+>-type semiconductor region 8, connecting the source and drain regions of n-channel MISFETs Q2, Q3, Q5, Q6, Q9, Q10, Q14, is formed below the p-channel regions thereof thus rendering the n-channel MISFETs Q2, Q3, Q5, Q6, Q9, Q10, Q14 depletion type. On the other hand, the semiconductor region 8 is not formed in the channel regions of other n-channel MISFETS Q1, Q4, Q7, Q8, Q11, Q12, Q13, Q15, Q16 thus rendering them enhancement type. |
