| 摘要 |
<p>An incrementing subtractive circuit for use in digital signal processing is constituted by a full adder (U1) having data inputs of which at least one is inverted, a sum output, and a carry output which is coupled by way of a half adder circuit (U3, U6) to a one bit upshifter (U2) at the carry input of the full adder. The one bit upshifter is controlled by a least significant bit control signal. The half adder includes a carry recirculation loop adapted to add a logical unity in response to the least significant bit control signal. The arrangement has the effect of adding integer two to the carry value of the fulle adder and achieves the additional incrementing necessary for to performance of incrementing subtraction or negating addition.</p> |
