| 摘要 |
<p>An output circuit of a sense amplifier for amplifying signals read out from a memory holds its output signals at predetermined levels stably in a state that equalizing pulses are being generated. Differential amplifiers (36a, 36b) amplify a pair of complementary signals read out from the memory. The output terminals of these differential amplifiers (36a, 36b) are connected to latch circuits (13, 14) via clocked inverter circuits (11, 12) and connected to transfer gates (N1, N2) controlled by equalizing pulses (EQ, EQ^¨B7). Since the clocked inverter circuits (11, 12) have high output impedance while the equalizing pulses are being generated, the signals held at the latch circuits (13, 14) do not change.</p> |
