| 摘要 |
<p>A random access memory device is equipped with a two-way power supplying system for distributing an external power voltage (Vext) level and an internal power voltage level (Vint) lower than the external power voltage level, and comprises a memory cell array (52) associated with a plurality of bit line pairs (BLP1 to BLPn) as well as with reference voltage lines (RF1 to RFm) shifted to a half of the internal power voltage level, a plurality of sense amplifier circuits (SA1 to SAn), a transfer gate unit (57) coupled between the bit line pairs and the sense amplifier circuits, and a timing controlling unit (56) for producing an activation signal fed to the sense amplifier circuits and a transfer gate controlling signal of the internal power voltage level fed to the transfer gate unit, wherein the activation signal is shifted to the external power voltage level so that the sense amplifier circuits rapidly increase small differences on the associated bit line pairs. <IMAGE></p> |
