Semiconductor memory device having means for repairing the memory device with respect to possible defective memory portions

摘要

A memory cell array (100) of an EPROM includes a first data memory region (1a), a second data memory region (1b), a 2M code memory line (2a) and a 1M code memory line (2b). When both the first and the second data memory regions (1a, 1b) are normal, the EPROM may be used as a 2M bit EPROM, in which case a device code indicating that the EPROM is a 2M bit EPROM is read out from the 2M code memory line (2a). When a defective portion is present in one of the first and the second data memory regions (1a, 1b), the EPROM may be used as a 1M bit EPROM, in which case a device code indicating that the EPROM is a 1M bit EPROM is read out from the 1M code memory line (2b).