| 摘要 |
The apparatus, in the protective mode, prevents the program and data in a memory region (1MB) of the real mode from being assigned to lower protective mode 1MB memory region. The apparatus includes a latch (90) for latching the address and control signals of a CPU (70) by the address latch enable signal, a tranceiver (100) for enabling and designating the flow direction of the data according to data enable signal and DR/Rbar signal, an I/O decoder (110) for generating indicator signal of mode change, an active signal latch circuit (120) for holding the protective mode active signal till the CPU is used by an user, a memory decoder (130) for generating the signal for as signing the memory using the protective mode setting latch signal transmitted from the protective mode active signal latch circuit 9120).
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