Address transition detector for programmable logic array
摘要
An improved address transition detector for use in PAL circuits is disclosed. The invention provides a predetermined logical output on a transition detection signal (TDS) bus for a transition of the input address on an input pad of the PAL. The TDS bus is used to trigger a phi generator which controls sense amplifiers and latch blocks on the PAL such that the circuitry is maintained in a low power stand-by mode. The detector includes a first inverter for buffering the address input to provide a first signal, a second inverter for inverting the first signal to provide a second signal and a comparator for providing the predetermined logical level on the TDS bus for a period of time after the first signal and the second signal have changed states.
申请公布号
US5057712(A)
申请公布日期
1991.10.15
申请号
US19890414312
申请日期
1989.09.29
申请人
ADVANCED MICRO DEVICE, INC.
发明人
TRINH, CUONG;WIN, VINCENT K. Z.;NOUBAN, BEHZAD;CHAN, ANDREW K.