| 摘要 |
For the processor having a synchronous bus, the feature of this scheme provides retrial circuitry to enhance reliability and performance before a reception processing upon accessing I/O device or memory. The retrial circuit (3) holds the fault signal (NAK-) insteads of passing to the processor (1), activates the circuit to stop the access start signal (MAS-) and tries to access I/ O device a desired number of times by applying (MAS-) signal again. Once finished to access with completion signal (ACK-) in fixed times, the circuit (3) sends completion flag (CACK-) to the processor. Otherwise it wends finally fault flag (CNAK-). The repetition times of trial can be selected by manufacturer. It is available also for DMA (Direct Memory Access) controller equipped device.
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