| 摘要 |
<p>PURPOSE:To prevent the erroneous discontinuation of a main system clock (SC) by controlling a main SC oscillation circuit with use of an AND secured between the output of an SC switch timing detection circuit and the output of an SC discontinuation flag. CONSTITUTION:A central arithmetic processing circuit outputs the addresses of an SC switch flag 7 and a main SC discontinuation flag 6 to an internal address bus 9 and also outputs the value (data) to be written to an internal data bus 8 respectively. An address decoder 10 decodes the value of the bus 9 and outputs a high level. Then the output of an AND gate 11 is set at a high level when a WR signal 12 is set at a high level. Then both flags 6 and 7 latch the value of the bus 8. An SC switch timing detection circuit 4 detects the switchable timing between a main SC and a sub-SC and synchronously latches a high level to output a high level to an AND gate 5. A selector 3 selects a subclock and switches the SCs. Meanwhile the output of the gate 5 is set at a high level and a high level is inputted to a main SC oscillation circuit 2 to discontinue the oscillation.</p> |
