SYNCHRONOUS WORD DETECTING SYSTEM

摘要

PURPOSE:To reduce the error detection rate of a synchronous word in a random bit sequence by permitting a line quality monitoring circuit to decide whether it is the random bit sequence or the bit sequence of a normal reception burst signal and outputting a synchronous word detection pulse. CONSTITUTION:A demodulation signal inputted from demodulation data input terminals 1 and 2 is correlation-detected in a synchronous word detection part 3 and is inputted to an AND circuit after it is delayed by the time corresponding to the processing time in the line quality monitoring circuit 4 by a delay circuit 8. On the other hand, a demodulation data input is inputted to an error correction circuit 5 an error is corrected, thereafter the input is encoded again with an encoder 9. The discordance of a signal string which is encoded again with the demodulation data input which is delayed by time corresponding to the processing time in the error correction circuit 5 and the encoder 9 is checked at every bit. When a discordance bit is generated, it is multiplied in a counter circuit 11 and multiplication is executed in one burst signal period. Then, it is decided whether the value exceeds a threshold or not in a comparator 12. The AND circuit 13 takes the AND of the synchronous word detection pulse and the output of the comparator 12 and outputs the final synchronous word detection pulse.