| 摘要 |
<p>PURPOSE:To prevent the runaway of a CPU even if a non-maskable interruption (NMI) is inputted at the time of a state that an NMI processing program is not set yet in the course of initial program loading (IPL) by inhibiting the input of the NMI in the course of IPL. CONSTITUTION:This system is provided with an NMI input inhibiting means 20 for inhibiting the input of an NMI to a CPU 10 from an interruption input device 14 in the course of IPL. That is, by a system reset signal SCLR, an NMI input inhibition/release flip-flop circuit 22 is reset, and the output signal of a positive phase data output terminal Q becomes an L level. Subsequently, a two-input NAND gate 23 becomes a state that it is inhibited to input the NMI to the NMI input terminal NMI of the CPU 10 from an interruption input device 14. In such a manner, even if the NMI is inputted at the time of a state that an NMI processing program is not set yet in the course of IPL, run away of the CPU 10 can be prevented, and the breakdown of a peripheral equipment caused by the runaway of the CPU 10 can be prevented.</p> |
