| 摘要 |
In a parallel processing system having a plurality of processors 1 (2, Fig 1), when an instruction word read out from a shared memory 3 and having control bits a, b associated with an indivisible operation is received by an instruction decoder 11, the control bits are supplied to an 3 indivisible-operation control circuit 7. If the control bits have values representing execution of the indivisible operation, the circuit 7 controls the indivisible operation via a sequencer 12 in accordance with the set/reset state of a flip-flop 13, which represents whether execution of the indivisible operation is assured. and with the level state of an indivisible-operation control line 9 to which all the processors are coupled. The indivisible operation is used to inhibit execution of asynchronous processing caused by an interrupt while a program is running. <IMAGE> |
