发明名称 DIGITAL PHASE CONTROL CIRCUIT
摘要 PURPOSE:To prevent production of out of synchronism even when a reproduction data with a peak shift is inputted by detecting a frequency difference based on a phase difference between an output clock and an input data and correcting the frequency of the output clock. CONSTITUTION:When an output of a phase difference detection circuit 12 is biased toward a negative value, that is, the frequency of the recovery data 103 is higher than the frequency of the output clock 104, a frequency difference detection circuit 13 detects that the frequency exceeds negatively a prescribed range and outputs a DOWN signal. A frequency division ratio setting circuit 14 changes the frequency division ratio by the DOWN signal, the frequency of the output clock 104 of a frequency divider circuit 15 approaches the frequency of the recovered data 101. Thus, out of synchronism is not caused to the output clock 104 even when the recovered data with a peak shift is inputted.
申请公布号 JPH03227123(A) 申请公布日期 1991.10.08
申请号 JP19900022639 申请日期 1990.01.31
申请人 NEC CORP 发明人 TAMURA KATSUSHI
分类号 G11B20/14;H03L7/06 主分类号 G11B20/14
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