| 摘要 |
PURPOSE:To prevent control over a controlled system from being disabled by processing input data in synchronism with a clock signal generated by the clock generating circuit of this device in response to a detection output when the reception stop of the clock is detected. CONSTITUTION:A clock pulse signal CK1 which is generated by the controller of the front-end stage is inputted to the controller 10 through a signal line 1. A clock monitor part 12 outputs a signal CM indicating that the signal CK1 is being received or its reception is stopped to a selector 13. Its clock generation part 11 generates and outputs a clock pulse signal CK2 to the selector 13. The selector 13 outputs the clock pulse signal CK1 or its clock signal CK2 selectively to a data processing part 14 according to the signal CM. Consequently, the control over the controlled system is prevented from being disabled. |
