| 摘要 |
The synchronisation device functions on the basis of recognition of the empty cells of an asynchronous link. It includes a circuit for searching for empty cells and a circuit for searching for the synchronisation status. A first comparator (2), associated with an input register, delivers a pulse at each header of an empty cell. This pulse is applied to a divide-by-two circuit (6, 7) via a first flip-flop (5). A counter (16) linked to the divide-by-two circuit, and reset to zero by the first flip-flop (5), is associated with an AND gate (15), also linked to the divide-by-two circuit, and to a second flip-flop (14); an output AND gate (13) linked to the first (5) and to the second (14) flip-flops delivers an empty-cell pulse to the circuit for searching for the synchronisation status. A second comparator (8), a NAND gate (9) and an AND gate (4) constitute a zero-reset circuit for the first flip-flop (5) and for the counter (16) when the comparator detects an error in the information field of an empty cell. The synchronisation search circuit includes a first RS flip-flop which receives the empty-cell pulses, a bit counter, a first flip-flop, two AND gates, a non-empty cell counter, a second flip-flop, a third AND gate and a second RS flip-flop, which delivers a synchronisation signal as soon as an empty cell is validated. The two RS flip-flops are reset to zero when the non-empty cell counter is full without any empty cell having been detected. <IMAGE>
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