| 摘要 |
PURPOSE:To provide resolution enough to drive a picture display device with high definition by adopting a polyphase clock for a clock transferring a data of a shift register of each system and frequency-dividing a clock of one phase in matching with a clock number at the inside of an integrated circuit so as to generate the polyphase clock. CONSTITUTION:A half bit shift register 1 is connected in multi-stage in one system and multi-stages of half-bit shift registers 2 of similar constitution are connected for shift registers of other system. Frequency dividers 3, 4 apply 1/N frequency division to one phase clocks C1, CL' respectively to generate N-phase clocks and a data DS is transferred in the shift registers by using clocks of phi1, phi2, phi3,... of one system and clocks phi1', phi2', phi3',... of the other system to transfer the data DS in the shift registers. A reset signal R is used to bring the frequency dividers into the initial state for a horizontal blanking period. The data switch 5 is sequentially turned on,off in the output timing of the shift registers of each half bit and a picture signal of a data line is sampled and held in a data capacitor 6. |
