发明名称 |
Clock digital multiplier. |
摘要 |
<p>A clock multiplier is selectable to provide either an unmultiplied input clock to the internal clock line or a multiplied clock signal, depending upon the state of a test mode input signal. By providing the circuitry on a integrated circuit chip, the chip can be driven at its normal operating frequency using lower-frequency test equipment. One multiplier device includes a plurality of series-connected one-shots. <IMAGE> <IMAGE></p> |
申请公布号 |
EP0449066(A1) |
申请公布日期 |
1991.10.02 |
申请号 |
EP19910104091 |
申请日期 |
1991.03.16 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
WENDELL, DENNIS L.;HOCHSTEDLER, CHARLES;LUNECKI, DAN;LYON, TERRY L. |
分类号 |
G11C29/00;G01R31/28;G11C29/56;H03K5/00 |
主分类号 |
G11C29/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|