| 摘要 |
PURPOSE:To realize a high-speed operation of a digital device, by constituting a carry foresight circuit for spontaneous carry and carry propagation discrimination bit of a small number with a small number of gate elements, the cloth wire and a read-only memory respectively. CONSTITUTION:Sum bit S1', the spontaneous carry bit G1 and the lower carrypropagation bit P1 of an addition are delivered through an ROM1. The lower 2-digit bit strings aL and bL are added with the lowest 2 digits of a bit signal CI thrugh an ROM2 between the addend and the augend. The bit string consisting of S1' and G0 is supplied with address into an ROM3 which obtains the sum S1 of a divisor 2<2> of upper 2 digits, and then S1 is registered. For the carry CO of the final adder, both G0 and P1 are supplied to an AND gate 4, and this output and G1 are added to an OR gate 5. For the time TCO when the CO is decided, the lower 2-bit S0 is fixed after the access time TACC of ROMs 1 and 2, and the upper 2 bits are fixed after the sum time of access time TACC' and TACC of an ROM3. An ROM connection of an 8-bit adder is simply carried out although a CLA circuit has 8 bits. |
