| 摘要 |
PURPOSE:To prevent the interruption of the high integration of LSI by setting the outputs of plural second latch circuits in plural storage circuits composed of two latch circuits to be the input signals of plural bits in the selection circuit of a post-stage. CONSTITUTION:When SEL 1 and 2 are both in 0-levels, the selection circuit 5 in the storage circuit 2 selects the output signal A10 of the storage circuit 1 in a pre-stage. A0 is transmitted to the output A10 of the circuit 5 and A0 is latched by a circuit 6 when the clock signal CK of the latch circuit 6 in the storage circuit 2 changes from '0' to '1'. When the clock signal ACK of a circuit 7 changes from '0' to '1', A0 is latched by the circuit 7. The shift of the outputs A0-A40 of the storage circuit completes by a series of an operation. Then, SEL 1 comes to '1', and SEL 2 to '0' and the operation similar to the operation is executed. A signal B0 is transmitted to the output S20 of the circuit 5, and B0 is stored in the circuit 6 when CK of the circuit in the circuit 2 changes from '0' to '1', whereby an output M20 comes to B0. When the signal BCK of the circuit 7 changes from '0' to '1', B0 is stored in the circuit 7 and the output B20 comes to B0. A series of the operation is repeated. |
