发明名称 SYNCHRONIZING SIGNAL GENERATING CIRCUIT
摘要 PURPOSE:To generate a highly accurate synchronizing signal by a simple circuit by specifying an address of a read-only memory stored previously with waveform data on a ternary level synchronizing signal, and converting the read data into the ternary level synchronizing signal and outputting it. CONSTITUTION:A carry signal generated when a clock counter 11 is reset is counted by a line counter 15, which is reset in response to the leading or trailing edge of a frame pulse 13 to acquire synchronism with an image frame. The output 12 of the clock counter 11 is used as a low-order address signal and the output 16 of the line counter 15 is used as a high-order address signal; and they are supplied to the read-only memory 19 stored previously with the waveform data on the ternary level synchronizing signal to read the waveform data on the ternary level synchronizing signal out of the read-only memory 19. Consequently, the highly accurate synchronizing signal can be generated by the simple circuit.
申请公布号 JPH03220981(A) 申请公布日期 1991.09.30
申请号 JP19900016881 申请日期 1990.01.26
申请人 FUJITSU GENERAL LTD 发明人 URATA EIKICHI
分类号 H04N5/06;H03K5/01;H03K5/125;H03M5/18;H04N7/00;H04N7/015;H04N7/08;H04N7/081 主分类号 H04N5/06
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