| 摘要 |
PURPOSE:To constitute a digital filter with CMOSes, by using an addition circuit having only to process addition in the processing unit split in one sampling period. CONSTITUTION:Signals X, Y, Z are split into three processing units of 3-bit, 3-bit, 2-bit, delay of 0, D and 2D is given with latches as much as the processing unit ranks higher, and adders A4, A5 and A6 are provided respectively. A carry output from the adder A6 is applied to an adder A7 via a latch and summed with a carry in the processing unit of the most significant rank of the output (X+Y). To cancel the delay given differently from the processing unit, delay of 0, 2D and 3D is given and the output in 10-bit is obtained. In the addition circuit mentioned above, since each adder has only to process addition in the processing unit in one sampling period, no high speed operation is required, allowing to use CMOSes. |
