| 摘要 |
PURPOSE:To minimize the number of steps for digit reduction or a saturation processing instruction by controlling the 1st and 2nd data memories, a logical operation circuit and a computing element by common program memory, program controller and address generator. CONSTITUTION:The 1st and 2nd data memories 12, 13, the logical operation circuit 20 and the arithmetic unit 14 are constituted so as to be controlled by the common program controller 15 and address generator 16. Thereby, the data (m) of the 2nd data memory 13 are read out on the way of transfer of data a' computed by the computing element 14 to the 1st data memory 12 and both the data m, m' are inputted to the circuit 20, so that the data a' is automatically deformed (digit reduction) by the data (m) and stored in the 1st data memory 12. Consequently, the number of steps for digit reduction or the saturation processing instruction can be minimized. |
