| 摘要 |
PURPOSE:To attain the reduction of a load on a CPU and the acceleration of reduction processing by performing the reduction of two-dimensional image information with the CPU, picture element information latch circuit consisting of simple latch circuit and gate circuit, and a picture element information gate circuit dispersively. CONSTITUTION:The CPU 1 judges whether or not the first picture element row of two-dimensional image information stored in a DRAM 2 is effective fitting in a thinning rate in a vertical direction. When it is the picture element row effective for it, the CPU 1 accumulates the picture element row of two bytes in two picture element information latch circuits 3, 4 from a first picture element via 8-bit data buses 8, 9 by issuing an instruction to address buses 6, 7. Furthermore, the CPU 1 generates thinning information of one byte by thinning the output data of the two picture element information latch circuits 3, 4 to 1/2, and inputs it by using 4-bit data buses 10, 11, and furthermore, inputs the thinning information from the picture element information gate circuit 5 which outputs data to the data bus 14 of the CPU 1 via a 8-bit data bus 13, and stores it in the DRAM 2. Thereby, the processing of the CPU 1 can be reduced. |
