| 摘要 |
The circuit for digital video signal processor includes a microprocessor (10) for generating the multiscreen selection signals (P4,P9,P13,P16), a memory (40), a multiscreen region setting circuit (20) for generating the screen region setting signal according to the multiscreen selection signals (P4,P9,P13,P16), and the value decider of the row address loading (30) for determining the initial value of row address matched to the signal (P4,P9,P13,P16) and the screen region setting signal. |
