| 摘要 |
PURPOSE:To eliminate phase difference between an original clock and a generated clock by delaying the original clock to eliminate the phase difference between the output clock of a dummy circuit provided in parallel with an output circuit and the original clock. CONSTITUTION:The original clock 2 is inputted to an FF 12 also to a CPU 1, and is converted to an internal clock 3 via a waveform arranging circuit 4 and a clock driver, and is used at an internal circuit 11, and also, is used as the strobe signal of an output latch 7. Therefore, a control signal 6 is varied at the leading edge of the internal clock 3, and is fetched in the FF 12 at the leading edge of the original clock 2. The internal clock 3 is fed back to a phase comparator 16 via a dummy output buffer 10, and the phase comparator 16 delays the original clock 2 by operating a voltage controlled delay element 18 so as to eliminate the phase difference between the original clock 2 and the output of the dummy output buffer 10. In such a way, the phase of the control signal 6 can be conformed to that of the original clock 2. |
