| 摘要 |
<p>A plurality of multiplicand bit transmission lines (a0 , a1 , ...) and a plurality of multiplier bit transmission lines (b0 , b1 , ...) or their decoding signal transmission lines (Bj) are arranged in a two-dimensional plane, and partial product generators (P) are arranged at their intersections. A plurality of rows of first multi-input adders (3W, 4W,...) are arranged at predetermined numbers of rows, and at least one row of second multi-input adders (4W, 6W,...) are arranged at predetermined numbers of the first multi-input adders. A basic cell (6D3 , ...) is formed by a predetermined number of partial product generators and one first multi-input adder, and the basic cells are repetitively arranged to obtain a rectangular configuration. <IMAGE></p> |
