| 摘要 |
<p>PURPOSE:To cope with various transmission packet rates with packet transmission circuits provided with reception buffers having the same capacity by determining the priority level of each circuit depending on the quantity of data stored in its transmission buffer with respect to the packet multiplexing device of a high speed packet switchboard. CONSTITUTION:Input data is successively stored in packet buffers 16 and 17 by a buffer switching circuit 20, and data is successively sent onto a bus line 1 through a selector 18 from buffers where data is stored on condition that the transmission right is acquired. The quantity of data stored in packet buffers is monitored by a data quantity counting circuit 22, and a transmission control circuit consisting of the selector 18, gates 19 and 24, and a bus contention circuit 23 gives a weight corresponding to this quantity of data to generate a priority level pattern for data transmission. This pattern is compared with a pattern or data transmitted on the bus line 1; and they coincide with each other, it is recognized that the pertinent circuit acquires the transmission right, and the bus contention circuit 23 designates output of data stored in packet buffers.</p> |
