发明名称 Repeater and PLL circuit
摘要 A PLL circuit for generating an AC output signal synchronized with an AC input signal applied thereto with a phase offset with respect to the input signal includes, in one embodiment, a charge pump circuit capable of varying the phase offset depending on the frequency of the AC input signal. In a signal transmission network system including a plurality of nodes coupled to a signal transmission line and distanced from one another by various repeat lengths of transmission path, each node has a repeater including such PLL circuit to suppress jitter caused by individual repeat length of transmission over the transmission line and still remaining in an equalized AC signal in each node.
申请公布号 US5052022(A) 申请公布日期 1991.09.24
申请号 US19890378281 申请日期 1989.07.11
申请人 HITACHI, LTD. 发明人 NISHITA, SHIGEO;YOSHINO, RYOZO;HIRAI, MASATO
分类号 H03L7/08;H04J3/06;H04L7/033;H04L12/42;H04L25/24;H04L25/52 主分类号 H03L7/08
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