| 摘要 |
PURPOSE:To save circuits unable to be integrated considerably by providing a circuit diciding a phase difference between an input clock and a retiming clock at a prescribed threshold level and inverting the phase of the retiming clock and a logic circuit comparing the state with the preceding retiming state of the decided signal. CONSTITUTION:This converter is provided with an n-multiple circuit 21 for an inputted clock, a frequency divider circuit 22 frequency-dividing an output of the circuit 21 into 1/n, an EX-OR state 23, and a multiplexing circuit 26 obtaining a multiplexing signal subjected to serial conversion. A parallel data signal inputted from a data input terminal 10 is subjected to retiming at a retiming circuit 24 and a phase difference detection circuit 25 detects that a timing margin of a phase difference between a clock signal 34 for retiming and the parallel data signal 31 is small, and the EX-OR gate 23 inverts the phase of the timing clock signal 34 when the timing margin is small. Thus, the retiming margin is increased more than that before the inversion and the production of an error due to the retiming is prevented. |
