发明名称 BUFFER CIRCUIT
摘要 <p>PURPOSE:To prevent transmission data in an unstable state from being taken in and to normally receive transmission data by taking in transmission data after inverting a clock in the case of approximation between the change point of transmission data and the data taking-in edge of the clock. CONSTITUTION:A data terminal equipment 10 sends transmission data SD to a data line terminating device 1 in accordance with a transmission signal element timing clock ST2 from the data line terminating device 1. A timing detecting part 5 of the terminating device 1 detects a timing difference Tx between a change point TS of the rise or the fall of data SD and a change point Tc of the rise of a clock ST2'' in the data line terminating device 1 which is generated by the same clock generation source as the clock ST2 and has 50% duty, and this detecting part 5 outputs '1' when the difference Tx approximates a preliminarily determined value. Then, a clock inversion control part 6 inverts the output clock to output the inverted clock of ST2''. That is, transmission data SD is taken in at the change point of the inverted clock of ST2'' to take in data SD in the stable state of an approximate center at the time of taking data SD into a first flip flop FF 2.</p>
申请公布号 JPH03217139(A) 申请公布日期 1991.09.24
申请号 JP19900012862 申请日期 1990.01.23
申请人 FUJITSU LTD 发明人 MATSUDA TAKAO
分类号 H04L25/40;G06F1/12;H04L7/027 主分类号 H04L25/40
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