发明名称 HIGHLY EFFICIENT CODER
摘要 PURPOSE:To improve the compression efficiency by sending an output of a block coding circuit, an additional code from a revision circuit and a bit number identification code from a decision circuit and eliminating a redundant part of the additional code generated in block coding. CONSTITUTION:Maximum value of a dynamic range DR and a minimum value MIN is detected from all blocks for one frame period. Assigned bit numbers n1, n2 to the DR and MIN are decided from the maximum value. The dynamic range DR and the minimum value MIN are revised into the bit numbers n1, n2. The additional code DR and MIN whose bit number is revised and an identification code DRn and MINn to identify the code signal DT and the bit number are sent. Thus, the redundant part of the additional code generated in the block coding is reduced and the transmission data quantity is reduced as a whole.
申请公布号 JPH03214987(A) 申请公布日期 1991.09.20
申请号 JP19900010364 申请日期 1990.01.19
申请人 SONY CORP 发明人 UCHIDA MASASHI
分类号 H04N19/115;H03M7/30;H04N1/41;H04N7/24;H04N19/00;H04N19/124;H04N19/126;H04N19/132;H04N19/136;H04N19/172;H04N19/174;H04N19/176;H04N19/196;H04N19/423;H04N19/46;H04N19/463;H04N19/60;H04N19/625;H04N19/65;H04N19/70;H04N19/98 主分类号 H04N19/115
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