发明名称 MEMORY TESTING DEVICE
摘要 PURPOSE:To control the inverted or uninverted state of the polarity of each bit of each pattern signal by providing selecting circuits which select and supply one of polarity control signals outputted by plural polarity control signal generators to polarity switches. CONSTITUTION:The signal selecting circuits 13A - 13N, and 23A - 23N are provided on the respective polarity control signal input sides of the polarity switches 12 and 22 provided on both the supply path 11 for a test pattern signal Tp and the supply path 21 for an expected value pattern signal Kp, and the circuits 13A - 13N and 23A - 23N select and extract one of the N input signals. Further, respective signal sources 41A - 41N of a polarity control signal generator 40 generate the polarity control signals P1 - PN corresponding to the respective bits of a memory 10 to be tested, and an inversion area and a noninversion area are prescribed by the bits of the memory 10 to be tested. Thus, the signal sources 41A - 41N of the generator 40 have patterns of various signals and the memory having inversion areas in various configurations can be tested.
申请公布号 JPH03215765(A) 申请公布日期 1991.09.20
申请号 JP19900009870 申请日期 1990.01.19
申请人 ADVANTEST CORP 发明人 HONMA TATSUYA;IMAI MINORU
分类号 G01R31/28;G06F11/22;G11C29/00;G11C29/56 主分类号 G01R31/28
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