| 摘要 |
PURPOSE:To enable high speed dynamic type memory cells to be integrated high in density by a method wherein a transfer gate electrode is provided around the wall face of a ring-shaped region which serves as a channel section, source/ drain diffusion layers are provided inside the ring-shaped region, and a part is exposed to serve as the contact region of bit lines. CONSTITUTION:An N-type first region 2' formed in the shape of a pillar to serve as a storage node electrode, an N-type second region 9 formed around the first region 2' through the intermediary of a capacitor film 8 to serve as a cell plate, and a P-type third region 3' formed on the first region 2' in a ring to serve as a channel region are included. A memory cell including a first conductor layer 11 formed around the third region 3' through the intermediary of an gate insulating film 10 to serve as a transfer gate electrode, an N-type fourth region 12 formed on a part of the third region 3', and a second conductor layer 14 formed in contact with the fourth region 12 to serve as a bit line is provided. By this setup, high speed dynamic type memory cells can be integrated high in density. |
