| 摘要 |
PURPOSE:To attain switching without error by deciding a write address for data storage unequivocally in correlation with a frame phase and while deciding uniquely a readout address independently of a duplex section. CONSTITUTION:A switching section 1A as shown in figure adds a pattern generated in a synchronizing pattern generating circuit 11 with respect to input data n-bit as a frame synchronizing pattern at a synchronizing pattern inserting circuit 12 to form outputs to duplex sections 2A, 2B. That is, a data of frame structure is sent to the duplex sections 2A, 2B as an output. On the other hand, an input data string being an input of frame structure is fed from the duplex section 2A to a synchronizing circuit 21A and a separate circuit 22A. Moreover, an input data string being an input of frame structure is fed from the duplex section 2B to a synchronizing circuit 21B and a separate circuit 22B. The circuit 21A takes synchronization by detecting a synchronizing pattern from an input data string from the duplex section 2A and the circuit 22A outputs separately the data string corresponding to the input data string accordingly. |
