| 摘要 |
PURPOSE:To enable the layout of logic cells where a wiring can easily be made to be obtained in a short time by a method wherein evaluation functions which evaluate the layout of logic cells are optimized on an average. CONSTITUTION:A setting section 1 sets evaluation functions which evaluate the layout of logic cells, the target value of each of the evaluation functions, a layout improvement method which makes the evaluation functions optimal, and a satisfaction level for each of the evaluation functions. A computation section 3 computes a difference between the evaluation function value obtained by evaluating the layout of the logic cells and the target value for each of the evaluation functions, and a selection section 3 selects an layout improvement method which optimizes the evaluation function corresponding to the maximum difference out of the computed differences. A execution section 7 executes the selected layout improvement method, and a resetting section 11 keeps the improved layouts of the logic cells if it is judged that the evaluation function value corresponding to the executed layout improvement method approximates to a target value and the evaluation function values other than the above function value satisfy a satisfaction level value. By this setup, the layout of logic cells where a wiring can be easily made can easily be obtained in a short time.
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