| 摘要 |
<p>PURPOSE:To correct a time difference among plural digital input signals with a same bit rate and a different phase by using one of a couple of storage means provided on every set of each signal for a write and using the other for a readout means and reading a data written already in a common clock timing simultaneously. CONSTITUTION:A clock signal from a 1st PLL circuit 11A is selected by a clock selecting circuit 14 and a readout address generating circuit selects a readout address of each RAM. Then a control signal from a RAM selective clock generating circuit 16 selects an output of RAMs 1, 3 whose write is already finished in each of a couple of RAMs at data selectors 13A, 13B and the selected output is transferred. Write is implemented to the other RAM 2 connecting to the input signal 1 in the timing when the data read of the RAMs 1, 3 is implemented and the write is implemented to the RAM 4 unused for the read of an input signal 2 after the lapse of time difference (t) from the write timing to the RAM 2.</p> |
