| 摘要 |
Multiple instruction queues (20) and a branch target cache (BTC) (180) of a high performance central processing unit (CPU) (18) design are integrated into a single physical structure. Effectively, the queues (20) are merged into the BTC (180) in such a manner that, at any point in time, most of this structure functions as BTC (180) while certain entries function as instruction queues. By using parts of the BTC (180) to serve as instruction queues, the inefficiency of separate queue structures is eliminated and the queues (20) are implemented with the greater device density characteristic of the RAM structures (170, 175, 180, 182) which the BTC (180) core is based on. This merging of these structures also substantially simplifies the instruction queue control and the routing of instruction words (190, 200, 220a, 220b, 220c) between BTC (180) entries and queues (20). |
