发明名称 MOS INTEGRATED CIRCUIT WITH ADJUSTABLE THRESHOLD VALUE
摘要 <p>PURPOSE: To obtain an integrated circuit having a threshold value adjustable within a wide extent of a voltage by method, wherein the basic structure of an electrically erasable programming memory call is utilized. CONSTITUTION: High voltage is applied between a drain D and a gate G, whereby a charge passes through a silicon oxide layer in a tunnel window and is stored under a floating gate FG. Such a cell has a property executable for the storage of the charge, that is erase (a state '1' that a transistor is turned on with respect to a read voltage VL) of a call and removal (a state '0' that the transistor is turned off with respect to the read voltage VL) of the charge under the floating gate FG due to a programming of the cell. The storage of the charge is equivalent to an application of an initial voltage to the floating gate FG, and the characteristic curve IDS=F(VG) of the cell is moved. The charge, which is stored under the floating gate FG, is controlled. Thereby, the threshold voltage of a device can be accurately controlled.</p>
申请公布号 JPH03214779(A) 申请公布日期 1991.09.19
申请号 JP19900192828 申请日期 1990.07.20
申请人 JIEMUPURIYUSU KAADE INTERNATL 发明人 JIYASETSUKU KOBUARUSUKII
分类号 G11C17/00;G11C11/56;G11C16/04;G11C16/10;H01L21/336;H01L21/8247;H01L27/115;H01L29/78;H01L29/788;H01L29/792 主分类号 G11C17/00
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